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CXP80712B/80716B/80720B/80724B
CMOS 8-bit Single Chip Microcomputer
Description The CXP80712B/80716B/80720B/80724B is a CMOS 8-bit microcomputer which consists of A/D converter, serial interface, timer/counter, time base timer, high precision timing pattern generation circuit, PWM output, VISS/VASS circuit, 32kHz timer/counter, remote control receiving circuit, VSYNC separator and the measurement circuit which measures signals of capstan FG and drum FG/PG and other servo systems, as well as basic configurations like 8-bit CPU, ROM, RAM and I/O port. They are integrated into a single chip. Also CXP80712B/80716B/80720B/80724B provides sleep/stop function which enables to lower power consumption. 100 pin QFP (PIastic) 100 pin LQFP (PIastic)
Structure Silicon gate CMOS IC
Features * A wide instruction set (213 instructions) which cover various types of data -- 16-bit arithmetic/multiplication and division/boolean bit operation instructions * Minimum instruction cycle 250ns at 16MHz operation 122s at 32kHz operation * Incorporated ROM capacity 12K bytes (CXP80712B) 16K bytes (CXP80716B) 20K bytes (CXP80720B) 24K bytes (CXP80724B) * Incorporated RAM capacity 800 bytes * Peripheral functions -- A/D converter 8 bits, 12 channels, successive approximation system (Conversion time of 20.0s/16MHz) -- Serial Interface Incorporated 8-bit and 8-stage FIFO, 1 channel (1 to 8 bytes auto transfer) 8-bit serial I/O, 1 channel -- Timer 8-bit timer 8-bit timer/counter 19-bit time base timer 32kHz timer/counter -- High precision timing pattern generator PPG for 19 pins, 32-stage programmable RTG for 5 pins, 2 channels -- PWM/DA gate output 12 bits, 2 channels (Repetitive frequency of 62.5kHz/16MHz) -- Servo input control Capstan FG, Drum FG/PG, CTL input -- VSYNC separator -- FRC capture unit Incorporated 26-bit and 8-stage FIFO -- PWM output 14 bits, 1 channel -- VISS/VASS circuit Pulse duty auto detection circuit -- Remote control receiving circuit 8-bit pulse measurement counter, 6-stage FIFO * Interruption 21 factors, 15 vectors, multi-interruption possible * Standby mode SLEEP/STOP * Package 100-pin plastic QFP/LQFP * Piggyback/evaluation chip CXP87700 100-pin ceramic PQFP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E95Z43A71
Block Diagram
NMI AVss INT0 INT1 INT2 TEX TX EXTAL XTAL RST MP VDD Vss
AVDD
AVREF
SPC700 CPU CORE
PORT B
CLOCK GENERATOR/ SYSTEM CONTROL 8
PORT A
AN0 to AN11 8
12
A/D CONVERTER
2
NMI
PA0 to PA7
CS0 SI0 SO0 SCK0 FIFO
PORT C
SERIAL INTERFACE UNIT (CH0)
PB0 to PB7
INTERRUPT CONTROLLER
SI1 SO1 SCK1 ROM 12K/16K/20K/24K BYTES RAM 800 BYTES
SERIAL INTERFACE UNIT (CH1)
8
PC0 to PC7
TO
8 BIT TIMER 1
PORT D
EC
8 BIT TIMER/COUNTER 0
8
PD0 to PD7
PORT E
SYNC0 SYNC1 2 2
V SYNC SEPARATOR
2 6 4 4
PE0 to PE1 PE2 to PE7 PF0 to PF3 PF4 to PF7
EXI0 EXI1
DRUM 3 FIFO FIFO FRC CAPTURE UNIT
SERVO INPUT CONTROL
RMC
REMOCON INPUT
32kHz TIMER/COUNTER
PORT G
CFG DFG DPG PBCTL
CTL
PORT F
PWM
14 BIT PWM GENERATOR
2
PORT H
12 BIT PWM GENERATOR CH0 2
PWM0 DAA0 DAB0 PWM1 DAA1 DAB1 PROGRAMMABLE PATTERN GENERATOR 4 2 19
RAM
REALTIME PULSE GENERATOR CH0 5 CH1
PORT I
ADJ
PPO0 to PPO18
RTO3 to RTO7
PORT J
-2-
CAPSTAN
PRESCALER/ TIME BASE TIMER
8
PG0 to PG7
DDO
VISS/VASS
8
PH0 to PH7
7
PI1 to PI7
CXP80712B/80716B/80720B/80724B
12 BIT PWM GENERATOR CH1
8
PJ0 to PJ7
CXP80712B/80716B/80720B/80724B
Pin Assignment 1 (Top View) 100 pin QFP package
PI3/TO/DDO/ADJ
PB6/PPO14
PB7/PPO15
PA0/PPO0
PA1/PPO1
PA2/PPO2
PA3/PPO3
PA4/PPO4
PA5/PPO5
PA6/PPO6
PA7/PPO7
PI4/INT1/NMI
VSS
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PB5/PPO13 PB4/PPO12 PB3/PPO11 PB2/PPO10 PB1/PPO9 PB0/PPO8 PC7/RTO7 PC6/RTO6 PC5/RTO5 PC4/RTO4 PC3/RTO3 PC2/PPO18 PC1/PPO17 PC0/PPO16 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PI6/SO1 PI7/SI1 PE0/INT0 PE1/EC/INT2 PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 PG0/CFG PG1/DFG PG2/DPG PG3/PBCTL PG4/SYNC0 PG5/SYNC1 PG6/EXI0 PG7/EXI1 AN0 AN1 AN2 AN3 PF0/AN4 PF1/AN5 PF2/AN6 PF3/AN7 AVDD AVREF AVSS PF4/AN8
TX
TEX
VDD
PI1/RMC
PI2/PWM
Note)
1. NC (Pin 90) is always connected to VDD. 2. Vss (Pins 41 and 88) are both connected to GND. 3. MP (Pin 39) is always connected to GND.
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PF7/AN11
PF6/AN10
PF5/AN9
EXTAL
SCK0
XTAL
RST
SO0
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
CS0
VSS
MP
SI0
PI5/SCK1
CXP80712B/80716B/80720B/80724B
Pin Assignment 2 (Top View) 100 pin LQFP package
PI3/TO/DDO/ADJ
PB4/PPO12
PB5/PPO13
PB6/PPO14
PB7/PPO15
PA0/PPO0
PA1/PPO1
PA2/PPO2
PA3/PPO3
PA4/PPO4
PA5/PPO5
PA6/PPO6
PA7/PPO7
PI4/INT1/NMI
PI5/SCK1
PI1/RMC
PI2/PWM
PI6/SO1
VSS
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PB3/PPO11 PB2/PPO10 PB1/PPO9 PB0/PPO8 PC7/RTO7 PC6/RTO6 PC5/RTO5 PC4/RTO4 PC3/RTO3 PC2/PPO18 PC1/PPO17 PC0/PPO16 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PD7 PD6 PD5 PD4 PD3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PE1/EC/INT2 PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 PG0/CFG PG1/DFG PG2/DPG PG3/PBCTL PG4/SYNC0 PG5/SYNC1 PG6/EXI0 PG7/EXI1 AN0 AN1 AN2 AN3 PF0/AN4 PF1/AN5 PF2/AN6 PF3/AN7 AVDD AVREF
TX
TEX
VDD
PF5/AN9
PF4/AN8
PI7/SI1
Note)
1. NC (Pin 88) is always connected to VDD. 2. Vss (Pins 39 and 86) are both connected to GND. 3. MP (Pin 37) is always connected to GND.
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PF7/AN11
PF6/AN10
EXTAL
SCK0
XTAL
AVSS
SO0
RST
PD2
PD1
PD0
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
CS0
VSS
SI0
MP
PE0/INT0
CXP80712B/80716B/80720B/80724B
Pin Description Symbol PA0/PPO0 to PA7/PPO7 I/O Output/ Real-time output (Port A) 8-bit output port. Data is gated with PPO contents by OR-gate and they are output. (8 pins) (Port B) 8-bit output port. Data is gated with PPO contents by OR-gate and they are output. (8 pins) (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. Data is gated with PPO or RTO contents by OR-gate and they are output. (8 pins) Description
PB0/PPO8 to PB7/PPO15 PC0/PPO16 to PC2/PPO18 PC3/RTO3 to PC7/RTO7
Output/ Real-time output I/O/ Real-time output I/O/ Real-time output
Programmable pattern generator (PPG) output. Functions as high precision real-time pulse output port. (19 pins)
Real-time pulse generator (RTG) output. Functions as high precision real-time pulse output port. (5 pins)
PD0 to PD7
I/O
(Port D) 8-bit I/O port. I/O can be set in a unit of 4 bits. Can 12mA sink current. (8 pins) Input pin to request external interruption. Active when falling edge. External event input pin for timer/counter. Input pin to request external interruption. Active when falling edge.
PE0/INT0
Input/Input
PE1/EC/INT2 PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 AN0 to AN3 PF0/AN4 to PF3/AN7 PF4/AN8 to PF7/AN11 SCK0 SO0 SI0 CS0
Input/Input/Input Output/Output Output/Output Output/Output Output/Output Output/Output Output/Output Input Input/Input (Port E) 8-bit port. Lower 2 bits are for inputs; upper 6 bits are for outputs. (8 pins)
PWM output pins. (2 pins)
DA gate pulse output pins. (4 pins)
Analog input pins to A/D converter. (12 pins) (Port F) Lower 4 bits are for inputs; upper 4 bits are for outputs. Lower 4 bits also serve as standby release input pin. (8 pins)
Output/Input I/O Ouput Input Input
Serial clock (CH0) I/O pin. Serial data (CH0) output pin. Serial data (CH0) input pin. Serial chip select (CH0) input pin.
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CXP80712B/80716B/80720B/80724B
Symbol PG0/CFG PG1/DFG PG2/DPG PG3/PBCTL PG4/SYNC0 PG5/SYNC1 PG6/EXI0 PG7/EXI1
I/O Input/Input Input/Input Input/Input Input/Input Input/Input Input/Input Input/Input Input/Input (Port G) 8-bit input port. (8 pins)
Description Capstan FG input pin. Drum FG input pin. Drum PG input pin. Playback CTL pulse input pin. Composite sync signal input pin. (2 pins) External input pin to FRC capture unit. (2 pins) (Port H) 8-bit output port; N-ch open drain output of medium drive voltage (12V) and large current (12mA). (8 pins) Remote control receiving circuit input pin. 14-bit PWM output pin. (Port I) 7-bit I/O port. I/O port can be set in a unit of single bits. (7 pins) Timer/counter, CTL duty detection, 32kHz oscillation adjustment output pin. Input pin to request external interruption and non maskable interruption. Active when falling edge. Serial clock (CH1) I/O pin. Serial data (CH1) output pin. Serial data (CH1) input pin. (Port J) 8-bit I/O port. Function as standby release input can be set in a unit of single bits. I/O can be set in a unit of single bits. Connecting pin of crystal oscillator for system clock. When supplying the external clock, input the external clock to EXTAL pin and input opposite phase clock to XTAL pin. Connecting pin of crystal oscillator for 32kHz timer clock. When used as event counter, input to TEX pin and leave TX pin open. (Feedback resistor is not removed.) System reset pin of active Low level. Test mode input pin. Always connect to GND. Positive power supply pin of A/D converter.
PH0 to PH7
Output
PI1/RMC PI2/PWM PI3/TO/ DDO/ADJ PI4/INT1/ NMI PI5/SCK1 PI6/SO1 PI7/SI1 PJ0 to PJ7 EXTAL XTAL TEX TX RST MP AVDD AVREF AVss VDD NC Vss
I/O/Input I/O/Output I/O/Output/ Output/Output I/O/Input/Input I/O/I/O I/O/Output I/O/Input I/O Input Output Input Output Input Input
Input
Reference voltage input pin of A/D converter. GND pin of A/D converter. Positive power supply pin. NC pin. Connect this pin to VDD for normal operation. GND pin. Connect both Vss pins to GND.
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CXP80712B/80716B/80720B/80724B
Input/Output Circuit Formats for Pins Pin Port A Port B PA0/PPO0 to PA7/PPO7 PB0/PPO8 to PB7/PPO15
PPO data
Circuit format
When reset
Ports A and B data
Hi-Z
Output becomes active from high impedance by data writing to port register.
Data bus RD (Ports A and B)
16 pins Port C
PC0/PPO16 to PC2/PPO18 PC3/RTO3 to PC7/RTO7
PPO, RTO data Port C data Input protection circuit IP
Hi-Z
Port C direction
Data bus RD (Port C)
8 pins Port D
PD0 to PD7
Port D data
Large current 12mA IP
Hi-Z
Port D direction
Data bus
8 pins
RD (Port D)
-7-
CXP80712B/80716B/80720B/80724B
Pin Port E
Circuit format
Schmitt input
When reset
PE0/INT0 PE1/EC/INT2
IP Data bus
Hi-Z
2 pins Port E
DA gate output PWM output
RD (Port E)
PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1
Hi-Z control Port E data
MPX
Hi-Z
Port/DA output select Data bus
4 pins Port E
RD (Port E)
DA gate output Hi-Z control MPX
PE6/DAB0 PE7/DAB1
Port E data
High level
Port/DA output select Data bus
2 pins
RD (Port E)
AN0 to AN3 4 pins Port F PF0/AN4 to PF3/AN7
Input multiplexer IP A/D converter
Hi-Z
Input multiplexer IP A/D converter
Hi-Z
Data bus
4 pins
RD (Port F)
-8-
CXP80712B/80716B/80720B/80724B
Pin Port F
Circuit format
When reset
PF4/AN8 to PF7/AN11
Port F data
Data bus RD (Port F) Port/AD select
Hi-Z
IP A/D converter
4 pins PG0/CFG PG1/DFG PG2/DPG PG3/PBCTL PG4/SYNC0 PG5/SYNC1 PG6/EXI0 PG7/EXI1 8 pins Port G
Schmitt input IP
Input multiplexer
Servo input Data bus RD (Port G)
Hi-Z
Note) For PG4/SYNC0 and PG5/SYNC1, CMOS schmitt input or TTL schmitt input can be selected with the mask option.
Port H PH0 to PH7
Medium drive voltage 12V
Port H data Data bus
Hi-Z
Large current 12mA
8 pins
RD (Port H)
Port I
Port I function select PI2: 14-bit PWM PI3: Timer/counter, CTL duty detection circuit, 32kHz timer Port I data Port I direction
PI2/PWM PI3/TO/ DDO/ADJ
MPX
Hi-Z
IP
Data bus
2 pins
RD (Port I)
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CXP80712B/80716B/80720B/80724B
PIn Port I
Port I data
Circuit format
When reset
PI1/RMC PI4/INT1/NMI PI7/SI1
Data bus
Port I direction IP RD (Port I)
Hi-Z
3 pins
PI1: Remote control circuit PI4: Interruption circuit PI7: Serial CH1
Schmitt input
Port I
Port I function select Serial CH1 Port I data Port I direction MPX Note) PI5 is schmitt input PI6 is inverter input RD (Port I) Serial CH1
PI5/SCK1 PI6/SO1
MPX
Hi-Z
IP
Data bus
2 pins Port J
Port J data
PJ0 to PJ7
Data bus
Port J direction
Hi-Z
IP RD (Port J) Standby release
Edge detection
8 pins
CS0 SI0 2 pins
Schmitt input
Hi-Z
IP Serial CH0
SO0
From Serial CH0
Hi-Z
1 pin
SO0 output enable
- 10 -
CXP80712B/80716B/80720B/80724B
PIn
Circuit format
When reset
Internal serial clock from serial CH0
SCK0
SCK0 output enable External serial clock to serial CH0 IP
Hi-Z
1 pin
Schmitt input
EXTAL XTAL
EXTAL
IP
* Shows the circuit composition during oscillation. * Feedback resistor is removed and XTAL becomes High level during stop.
Oscillation
2 pins
XTAL
32kHz timer counter
TEX TX
TEX
IP
2 pins
TX
* Shows the circuit composition during oscillation. * Feedback resistor is removed during 32kHz oscillation circuit stop by software. At this time TEX pin outputs Low level and TX pin outputs High level.
Oscillation
Mask option
Pull-up resistor Schmitt input
RST
OP
Low level
IP
1 pin
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CXP80712B/80716B/80720B/80724B
Absolute Maximum Ratings Item Symbol VDD Supply voltage AVDD AVSS Input voltage Output voltage Medium drive output voltage High level output current High level total output current Low level output current VIN VOUT VOUTP IOH IOH IOL IOLC Low level total output current Operating temperature Storage temperature Allowable power dissipation IOL Topr Tstg PD Rating -0.3 to +7.0 AVss to +7.01 -0.3 to +0.3 -0.3 to +7.01 -0.3 to +7.01 -0.3 to +15.0 -5 -50 15 20 130 -20 to +75 -55 to +150 600 380 mW Unit V V V V V V mA mA mA mA mA C C QFP package type LQFP package type Total of output pins Port H (PH) Remarks
(Vss = 0V)
Other than large current output port (value per pin) Large current port2 (value per pin) Total of output pins
1 AVDD, VIN and VOUT must not exceed VDD + 0.3V. 2 The large current output ports are Port D (PD) and Port H (PH). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should better take place under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI.
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CXP80712B/80716B/80720B/80724B
Recommended Operating Conditions Item Symbol Min. 4.5 3.5 2.7 2.5 Analog power supply AVDD VIH HIgh level input voltage VIHS VIHTS VIHEX VIL Low level input voltage VILS VILTS VILEX Operating temperature Topr 4.5 0.7VDD 0.8VDD 2.2 Max. 5.5 5.5 5.5 5.5 5.5 VDD VDD VDD Unit V V V V V V V V V V V V V C Remarks
(Vss = 0V)
Guaranteed operation range for 1/2, 1/4 frequency dividing clock Guaranteed operation range for 1/16 frequency dividing clock or during SLEEP mode. Guaranteed operation range by TEX clock Guaranteed data hold operation range during STOP 1 2 CMOS schmitt input3 TTL schmitt input4 EXTAL pin5 TEX pin6 2 CMOS schmitt input3 TTL schmitt input4 EXTAL pin5 TEX pin6
Supply voltage
VDD
VDD - 0.4 VDD + 0.3 0 0 0 -0.3 -20 0.3VDD 0.2VDD 0.8 0.4 +75
1 AVDD and VDD should be set to the same voltage. 2 Normal input port (each pin of PC, PD, PE0, PE1, PF0 to PF3, PG, PI and PJ), MP pin. 3 Each pin of CS0, SI0, SCK0, RST, PE0/INT0, PE1/EC/INT2, PG (For PG4 and PG5, when CMOS schmitt input is selected with mask option), PI1/RMC, PI4/INT1/NMI, PI5/SCK1 and PI7/SI1. 4 Each pin of PG4 and PG5 (When TTL schmitt input is selected with mask option) 5 Specifies only during external clock input. 6 Specifies only during event count clock input.
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CXP80712B/80716B/80720B/80724B
Electrical Characteristics DC Characteristics Item High level output voltage Low level output voltage Symbol VOH Pins PA to PD, PE2 to PE7, PF4 to PF7, PH (VOL only) PI1 to PI7 PJ, SO0, SCK0 PD, PH IIHE IILE Input current IIHT IILT IILR TEX RST1 PA to PG, PI, PJ, MP AN0 to AN3, CS0, SI0, SO0 SCK0, RST1 EXTAL Conditions VDD = 4.5V, IOH = -0.5mA VDD = 4.5V, IOH = -1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V 0.5 -0.5 0.1 -0.1 -1.5 (Ta = -20 to +75C, Vss = 0V) Min. 4.0 3.5 0.4 0.6 1.5 40 -40 10 -10 -400 Typ. Max. Unit V V V V V A A A A A
VOL
I/O leakage current
IIZ
VDD = 5.5V, VI = 0, 5.5V
10
A
Open drain output leakage current (N-CH Tr off state)
ILOH
PH
VDD = 5.5V VOH = 12V 16MHz crystal oscillation (C1 = C2 = 15pF), VDD = 5.5V 16MHz crystal oscillation (C1 = C2 = 15pF), VDD = 5.5V, SLEEP mode
50
A
IDD1
20
45
mA
IDDS1 Supply current2
1.1
8
mA
IDD2
VDD
32kHz crystal oscillation (C1 = C2 = 47pF), VDD = 3.3V 32kHz crystal oscillation (C1 = C2 = 47pF), VDD = 3.3V, SLEEP mode VDD = 5.5V, STOP mode (termination of 32kHz and 16MHz crystal oscillation)
35
100
A
IDDS2
7
30
A
IDDS3
10
A
Input capacity
CIN
PC, PD, PE0 to 1, PF0 to 3, PG, PI, PJ, AN, Clock 1MHz SCK0, SI0, 0V other than the measured pins CS0, EXTAL, XTAL, TEX, TX, RST, MP
10
20
pF
1 RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current when no resistance is selected. 2 When entire output pins are open. 3 When setting upper 2 bits (CPU clock selection) of clock control register (CLC: 00FEH) to "00" and operating in high speed mode (1/2 frequency dividing clock). - 14 -
CXP80712B/80716B/80720B/80724B
AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rise and fall times Event count clock input pulse width Event count clock input rise and fall times System clock frequency Event count clock input pulse width Event count clock input rise and fall times 1 Symbol fC Pins XTAL EXTAL XTAL EXTAL XTAL EXTAL EC EC TEX TX TEX TEX Fig. 1, Fig. 2
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V) Conditions Min. 1 28 200 4tsys1 20 32.768 10 20 Typ. Max. Unit 16 MHz ns ns ns ns kHz s ms
tXL, tXH tCR, tCF tEH, tEL tER, tEF
fC
Fig. 1, Fig. 2 (External clock drive) Fig. 1, Fig. 2 (External clock drive) Fig. 3 Fig. 3 Fig. 2 VDD = 2.7 to 5.5V (32kHz clock applied condition) Fig. 3 Fig. 3
tTL, tTH tTR, tTF
tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper 2 bits
(CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Fig. 1. Clock timing
1/fc
VDD - 0.4V EXTAL 0.4V tXH tCF tXL tCR
Fig. 2. Clock applied condition
Crystal oscillation Ceramic oscillation External clock 32kHz clock applied condition crystal oscillation
EXTAL C1
XTAL C2
EXTAL
XTAL C1
TEX
TX C2
74HC04
Fig. 3. Event count clock timing
0.8VDD 0.2VDD tEH tTH tEF tTF tEL tTL tER tTR
TEX EC
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CXP80712B/80716B/80720B/80724B
(2) Serial transfer (CH0) Item CS0 SCK0 delay time CS0 SCK0 float delay time CS0 SO0 delay time CS0 SO0 float delay time CS0 High level width SCK0 cycle time SCK0 High and Low level widths SI0 input setup time (for SCK0 ) SI0 input hold time (for SCK0 ) SCK0 SO0 delay time Note 1) Symbol Pin SCK0
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V) Condition Chip select transfer mode (SCK0 = output mode) Chip select transfer mode (SCK0 = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode SCK0 Output mode Input mode SCK0 Output mode SCK0 input mode SI0 SCK0 output mode SCK0 input mode SI0 SCK0 output mode SCK0 input mode SO0 SCK0 output mode Min. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
tDCSK
tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys + 200
2tsys + 200 16000/fc
tDCSKF SCK0 tDCSO
SO0
tDCSOF SO0 tWHCS CS0 tKCY tKH tKL tSIK tKSI tKSO
tsys + 100
8000/fc - 50 100 200
tsys + 200
100
tsys + 200
100
ns ns
tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper
2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF + 1TTL.
- 16 -
CXP80712B/80716B/80720B/80724B
Fig. 4. Serial transfer timing (CH0)
tWHCS
CS0 0.8VDD
0.2VDD
tKCY tDCSK tKL tKH tDCSKF
0.8VDD SCK0 0.2VDD
0.8VDD
tSIK
tKSI
0.8VDD SI0 Input data 0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD SO0 Output data 0.2VDD
- 17 -
CXP80712B/80716B/80720B/80724B
Serial transfer (CH1) Item SCK1 cycle time SCK1 High and Low level widths SI1 input setup time (for SCK1 ) SI1 input hold time (for SCK1 ) SCK1 SO1 delay time Symbol Pins SCK1
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V) Conditions Input mode Output mode Input mode SCK1 Output mode SCK1 input mode SI1 SCK1 output mode SCK1 input mode SI1 SCK1 output mode SCK1 input mode SO1 SCK1 output mode Min. 1000 16000/fc 400 8000/fc - 50 100 200 200 100 200 100 Max. Unit ns ns ns ns ns ns ns ns ns ns
tKCY tKH tKL tSIK tKSI tKSO
Note) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL.
Fig. 5. Serial transfer timing (CH1)
tKCY tKL tKH
SCK1
0.8VDD
0.2VDD
tSIK
tKSI
0.8VDD SI1 Input data 0.2VDD
tKSO
0.8VDD SO1 0.2VDD Output data
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CXP80712B/80716B/80720B/80724B
(3) A/D converter characteristics (Ta = -20 to +75C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V) Item Resolution Linearity error Absolute error Conversion time Sampling time Ta = 25C VDD = AVDD = AVREF = 5.0V VSS = AVSS = 0V Symbol Pins Conditions Min. Typ. Max. 8 1 2 160/fADC1 12/fADC1 AVREF AN0 to AN11 Operating mode AVREF IREFS SLEEP mode STOP mode 32kHz operating mode AVDD - 0.5 0 0.6 AVDD AVREF 1.0 10 Unit Bits LSB LSB s s V V mA A
tCONV tSAMP
VIAN IREF
Reference input voltage VREF Analog input voltage
AVREF current
Fig. 6. Definitions of A/D converter terms
FFH FEH
Digital conversion value
1 fADC indicates the below values due to the contents of bit 0 (ADCCK) of the ADC operation clock selection (MSC: 01FFH), bits 7 (PCK1) and 6 (PCK0) of the clock control register. ADCCK PCK1, PCK0
Linearity error
0 (/2 selection) fADC = fC/2 fADC = fC/4 fADC = fC/16
1 ( selection) fADC = fC fADC = fC/2 fADC = fC/8
00 ( = fEX/2) 01 ( = fEX/4)
01H 00H VZT Analog input VFT
11 ( = fEX/16)
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CXP80712B/80716B/80720B/80724B
(4) Interruption, reset input Item Symbol
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V) Pins INT0 INT1 INT2 NMI PJ0 to PJ7 RST Conditions Min. Max. Unit
External interruption High and Low level widths
tIH tIL tRSL
1
s
Reset input Low level width
32/fc
s
Fig. 7. Interruption input timing
INT0 INT1 INT2 NMI PJ0 to PJ7 (During standby release input) (Falling edge)
tIH
tIL
0.8VDD 0.2VDD
Fig. 8. Reset input timing
tRSL
RST 0.2VDD
(5) Others Item CFG input High and Low level widths Symbol Pins CFG DFG DPG DPG PBCTL EXI0 EXI1
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V) Conditions Min. Max. Unit ns ns ns ns ns ns
tCFH tCFL tDFH DFG input High and Low level widths tDFL DPG minimum pulse width tDPW
DPG minimum removal time PBCTL input High and Low level widths
tFRC x 24 + 200 tFRC x 8 + 200
50 50
trem
tCTH tCTL tEIH EXI input High and Low level widths tEIL
Note) bits (CPU clock selection).
tsys = 2000/fc tsys = 2000/fc
tFRC x 8 + 200 + tsys tFRC x 8 + 200 + tsys
tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper 2 tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") tFRC [ns] = 1000/fc
- 20 -
CXP80712B/80716B/80720B/80724B
Fig. 9. Other timings
tCFH tCFL
0.8VDD CFG 0.2VDD
tDFH
tDFL
0.8VDD DFG 0.2VDD
trem
tDPW
trem
0.8VDD DPG
tCTH
tCTL
0.8VDD PBCTL 0.2VDD
tEIH
tEIL
EXI0 EXI1
0.8VDD 0.2VDD
- 21 -
CXP80712B/80716B/80720B/80724B
Appendix Fig. 10. Recommended oscillation circuit
(i) (ii)
EXTAL
XTAL Rd
TEX
TX Rd
C1
C2
C1
C2
Manufacturer
Model
fc (MHz) 8.00
C1 (pF) 10
C2 (pF) 10
Rd ()
Circuit example
RIVER ELETEC CO., LTD.
HC-49/U03
10.00 12.00 16.00 8.00 5 16 16 12 12 30 5 12 12 12 12 18
0
(i)
KINSEKI LTD.
HC-49/U (-S)
10.00 12.00 16.00
0
(i)
P3
32.768kHz
470k
(ii)
Mask option table Item Reset pin pull-up resistor Input circuit format1 Content Non-existent C-MOS schmitt Existent TTL schmitt
1 The input circuit format can be selected for PG4/SYNC0 pin and PG5/SYNC1, respectively.
- 22 -
CXP80712B/80716B/80720B/80724B
Characteristics Curve
IDD vs. VDD
(fc = 16MHz, Ta = 25C, Typical) 20.0 10.0 1/2 dividing mode 1/4 dividing mode 1/16 dividing mode 20
IDD vs. fC
(VDD = 5V, Ta = 25C, Typical)
1/2 dividing mode
SLEEP mode 1.0 0.5 32kHz mode (instruction) 32kHz SLEEP mode
IDD - Supply current [mA]
IDD - Supply current [mA]
5.0
15
10
1/4 dividing mode
0.1 (100A) 0.05 (50A)
5 1/16 dividing mode 0.01 (10A) 2 3 4 5 6 7 0 5 10 fc - System clock [MHz] SLEEP mode 16
VDD - Supply voltage [V]
- 23 -
CXP80712B/80716B/80720B/80724B
Package Outline
Unit: mm
100PIN QFP (PLASTIC)
+ 0.1 0.15 - 0.05
23.9 0.4 + 0.4 20.0 - 0.1
+ 0.4 14.0 - 0.01 17.9 0.4
15.8 0.4
A
0.65 0.12 M
+ 0.35 2.75 - 0.15
0.15
0 to 15 DETAIL A
0.8 0.2
(16.3)
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-100P-L01 QFP100-P-1420-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 1.4g
100PIN LQFP (PLASTIC)
16.0 0.2 75 76 14.0 0.1 51 50
100 1 0.5 0.08 + 0.08 0.18 - 0.03 25
26 (0.22)
+ 0.2 1.5 - 0.1
+ 0.05 0.127 - 0.02 0.1
0.1 0.1
0 to 10
DETAIL A
0.5 0.2
NOTE: Dimension "" does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY/PHENOL RESIN SOLDER PLATING 42 ALLOY LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT
SONY CODE EIAJ CODE JEDEC CODE
LQFP-100P-L01 QFP100-P-1414-A
- 24 -
0.5 0.2
A
(15.0)

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